? semiconductor components industries, llc, 2001 october, 2001 rev. 7 1 publication order number: sn74ls259/d sn74ls259 8-bit addressable latch the sn74ls259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. it is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active high outputs. the device also incorporates an active low common clear for resetting all latches, as well as, an active low enable. ? serial-to-parallel conversion ? eight bits of storage with output of each bit available ? random (addressable) data entry ? active high demultiplexing or decoding capability ? easily expandable ? common clear guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 0.4 ma i ol output current low 8.0 ma low power schottky soic d suffix case 751b plastic n suffix case 648 16 1 16 1 soeiaj m suffix case 966 16 1 device package shipping ordering information sn74ls259n 16 pin dip 2000 units/box sn74ls259d soic16 38 units/rail sn74ls259dr2 soic16 2500/tape & reel sn74ls259m soeiaj16 see note 1 sn74ls259mel soeiaj16 1. for ordering information on the eiaj version of the soic package, please contact your local on semiconductor representative. see note 1 http://onsemi.com
sn74ls259 http://onsemi.com 2 connection diagram dip (top view) address inputs data input enable (active low) input clear (active low) input parallel latch outputs a 0 , a 1 , a 2 d e c q 0 - q 7 0.5 u.l. 0.5 u.l. 1.0 u.l. 0.5 u.l. 10 u.l. 0.25 u.l. 0.25 u.l. 0.5 u.l. 0.25 u.l. 5 u.l. notes: a) 1 ttl unit load (u.l.) = 40 a high/1.6 ma low. high low (note a) loading pin names 14 13 12 11 10 9 123456 7 16 15 8 v cc a o c e dq 7 q 5 q 6 q 4 a 1 a 2 q 0 q 1 q 2 q 3 gnd
e c mode l h l h h h l l addressable latch memory active high eight-channel demultiplexer clear mode selection x = don't care condition l = low voltage level h = high voltage level q n1 = previous output state sn74ls259 http://onsemi.com 3 logic diagram e da 0 a 1 a 2 c q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 14 12 67 3 4 5 9 11 12 10 13 15 v cc = pin 16 gnd = pin 8 = pin numbers functional description the sn74ls259 has four modes of operation as shown in the mode selection table. in the addressable latch mode, data on the data line (d) is written into the addressed latch.the addressed latch will follow the data input with all non-addressed latches remaining in their previous states. in the memory mode, all latches remain in their previous state and are unaffected by the data or address inputs. in the one-of-eight decoding or demultiplexing mode, the addressed output will follow the state of the d input with all other inputs in the low state. in the clear mode all outputs are low and unaffected by the address and data inputs. when operating the sn74ls259 as an addressable latch, changing more then one bit of the address could impose a transient wrong address. therefore, this should only be done while in the memory mode. the truth table below summarizes the operations. truth table present output states c e d a 0 a 1 a 2 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 mode l h x x x x l l l l l l l l clear l ll l l l l l l l l l l l demultiplex l lh l l l h lllllll l ll h l l l lllllll l lh h l l l hllllll ? ?? ? ? ? ?? ? ? ? ?? ? ? ? ?? ? ? ? ?? ? ? l lh h h h l llllllh h h x x x x q n1 memory h i i l l l l q n1 q n1 q n1 addressable h lh l l l h q n1 q n1 latch h ll h l l q n1 lq n1 h lh h l l q n1 hq n1 ? ?? ? ? ? ?? ? ? ? ?? ? ? ? ?? ? ? ? ?? ? ? h ll h h h q n1 q n1 l h l h h h h q n1 q n1 h
sn74ls259 http://onsemi.com 4 dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v ol out p ut low voltage 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in v il or v ih v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v in = v il or v ih per truth table i ih in p ut high current 20 m a v cc = max, v in = 2.7 v i ih input high current 0.1 ma v cc = max, v in = 7.0 v i il input low current 0.4 ma v cc = max, v in = 0.4 v i os short circuit current (note 2) 20 100 ma v cc = max i cc power supply current 36 ma v cc = max 2. not more than one output should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c, v cc = 5.0 v) limits symbol parameter min typ max unit test conditions t plh t phl turn-off delay, enable to output turn-on delay, enable to output 22 15 35 24 ns ns t plh t phl turn-off delay, data to output turn-on delay, data to output 20 13 32 21 ns ns c l = 15 pf t plh t phl turn-off delay, address to output turn-on delay, address to output 24 18 38 29 ns ns c l = 15 f t phl turn-on delay, clear to output 17 27 ns ac set-up requirements (t a = 25 c, v cc = 5.0 v) limits symbol parameter min typ max unit t s input setup time 20 ns t w pulse width, clear or enable 15 ns t h hold time, data 5.0 ns t h hold time, address 20 ns
sn74ls259 http://onsemi.com 5 t s figure 1. turn-on and turn-off delays, enable to output and enable pulse width figure 2. turn-on and turn-off delays, data to output figure 3. turn-on and turn-off delays, address to output notes: 1. the address to enable setup time is the time before the high-to-low enable transition that the address must be stable so tha t the correct latch is addressed and the other latches are not affected. 2. the shaded areas indicate when the inputs are permitted to change for predictable output performance. other conditions: c = h, a = stable other conditions: e = l, c = h, a = stable other conditions: e = l, c = l, d = h other conditions: c = h, a = stable other conditions: e = h 1.3 v t phl t plh 1.3 v d e q 1.3 v 1.3 v 1.3 v 1.3 v t plh t phl d q 1.3 v 1.3 v t phl c q 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v a 1 a 1 q 1 t plh d e q t h (h) t h (l) 1.3 v other conditions: c = h stable address a e t s (h) t s (l) t phl t w t w q=d q=d ac waveforms figure 4. setup and hold time, data to enable figure 5. turn-on delay, clear to output figure 6. setup time, address to enable (see notes 1 and 2)
sn74ls259 http://onsemi.com 6 package dimensions n suffix plastic package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
sn74ls259 http://onsemi.com 7 package dimensions d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
sn74ls259 http://onsemi.com 8 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z m suffix soeiaj package case 96601 issue o on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. sn74ls259/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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